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? semiconductor components industries, llc, 2015 june, 2018 ? rev. 0 1 publication order number: FUSB301A/d FUSB301A autonomous usb type-c controller with configurable i 2 c address description the FUSB301A is a fully autonomous type-c controller optimized for < 15 w applications. the FUSB301A offers cc logic detection for source mode, sink mode, drp, accessory detection support, and dead battery support. the FUSB301A features configurable i 2 c address tosupport multiple ports per system. the FUSB301A features an extremely low power disable mode as well as low power during normal operation. it is available in an ultra thin, 12-lead tmlp package. features ? fully autonomous type ? c controller supports type ? c versions 1.1 and 1.0 ? v dd operating range, 3.0 v ? 5.5 v ? low disable power: i cc = 2.0 a (max.) ? low standby power: i cc = 7.0 a (max.) ? drp mode with optional accessory support ? configurable i 2 c address ? capable of supporting try.snk and try.src ? dead battery support (sink support when no power applied) ? 2 kv hbm esd protection ? small packaging, 12 lead tmlp (1.6 mm 1.6 mm 0.375 mm) applications ? smartphones ? tablets ? notebooks ? ultra portable applications figure 1. typical application www. onsemi.com see detailed ordering and shipping information on page 2 of this data sheet. ordering information x2qfn12 1.6x1.6, 0.4p case 722ad bottom view
FUSB301A www. onsemi.com 2 ordering information part number top mark operating temperature range package packing method ? FUSB301A nx ? 40 to 85 c 12 ? lead ultra ? thin molded leadless package (tmlp) 1.6 mm 1.6 mm 0.375 mm tape and reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d . block diagram figure 2. block diagram pin configuration figure 3. pin assignment (top through view)
FUSB301A www. onsemi.com 3 pin descriptions pin # name type description usb type ? c connector interface 1, 2 cc1, cc2 i/o type ? c configuration channel 4 vbus input vbus input pin for attach and detach detection 10 gnd ground ground power interface 12 vdd power input supply voltage signal interface 8 scl input i 2 c serial clock signal to be connected to the i 2 c master 7 sda open ? drain i/o i 2 c serial data signal to be connected to the i 2 c master 6 int_n open ? drain output active low open drain interrupt output used to prompt the processor to read the i 2 c register bits 9 id open ? drain output used to identify if connected device is source or sink. the id pin can be used to interface with usb 2.0 input on the processor. 5 i2caddr input used to change bit 3 of the i2c address so that multiple addresses can be used in a system where two device addresses conflict 3 nc1 nc no connect ? tie to ground or float 11 nc2 nc no connect ? tie to ground or float dead battery if power is not applied to FUSB301A and it is attached to a source device, then the source would pull up the cc line connected through the cable. the FUSB301A in response would turn on the pull ? down that will bring the cc voltage to a range that the source can detect an attach and turn on vbus. power up, initialization and reset, interrupt operation when power is first applied, the FUSB301A will power up in sink mode with all interrupts masked. the local processor must configure the FUSB301A to the desired mode and clear the global interrupt mask bit, int_mask. the int_n pin is an active low, open drain output. this pin indicates to the host processor that an interrupt has occurred in the FUSB301A which needs attention. the int_n pin is in a high impedance state by default after power ? up or device reset, and the global interrupt mask (int_mask in control register) is set. after int_mask bit is cleared by the local processor, the int_n pin stays high impedance in preparation of future interrupts. when an interruptible event occurs, int_n is driven low and is in a high impedance state again when the processor clears the interrupt by reading the interrupt registers. subsequent to the initial power up or reset; if the processor writes a ?1? to global interrupt mask bit when the system is already powered up, the int_n pin stays in a high impedance state and ignores all interrupts until the global interrupt mask bit is cleared. if an event happens that would ordinarily cause an interrupt when the global interrupt mask bit is set, the int_n pin goes low when the global interrupt mask is cleared. table 1. id pin truth table type register (h12, bit 4) description id sink = b0 sink not detected hi ? z (default) sink = b1 sink detected low absolute maximum ratings symbol parameter min. max. unit v dd supply voltage from v dd ? 0.5 6.0 v v bus vbus supply voltage ? 0.5 28 v v cc_hddrp cc pins when configured as host, device or dual role port ? 0.5 6.0 v t storage storage temperature range ? 65 +150 c
FUSB301A www. onsemi.com 4 absolute maximum ratings (continued) symbol unit max. min. parameter t j maximum junction temperature +150 c t l lead temperature (soldering, 10 seconds) +260 c esd iec 6100 ? 4 ? 2 system esd connector pins (vbus, cc1 and cc2) air gap 15 kv contact 8 human body model, jedec jesd22 ? a114 connector pins (vbus, cc1 and cc2) 4 others 2 charged device model, jedec lesd22 ? c101 all pins 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. recommended operaing conditions symbol parameter min. typ. max. unit v bus vbus supply voltage 3.7 5.0 21 v v dd supply voltage 2.8 (1) 3.3 5.5 v t a operating temperature ? 40 +85 c 1. this is for functional operation only and isn?t the lowest limit for all subsequent electrical specifications below. all electrical par ameters have a minimum of 3 v operation. dc and transient characteristics unless otherwise specified: recommended t a and t j temperature ranges. all typical values are at t a = 25 c and v dd = 3.3 v unless otherwise specified. symbol parameter t a = ? 40 to +85 c t j = ? 40 to +125 c unit min. typ. max. type c specific parameters i 80_ccx source 80 a cc current (default) host_cur1 = 0, host_cur0 = 1 64 80 96 a i 180_ccx source 180 a cc current (1.5 a) host_cur1 = 1, host_cur0 = 0 166 180 194 a i 330_ccx source 330 a cc current (3 a) host_cur1 = 1, host_cur0 = 1 304 330 356 a v snkdb sink pull ? down voltage in dead battery under all pull ? up source loads 2.18 v r device sink pull ? down resistance when v dd is within operating range 4.6 5.1 5.6 k zopen cc resistance for disabled state 126 k vra ? srcdef ra detection threshold for cc pin for source for default current on vbus 0.15 0.20 0.25 v vra ? src1.5a ra detection threshold for cc pin for source for 1.5 a current on vbus 0.35 0.40 0.45 v vra ? src3a ra detection threshold for cc pin for source for 3 a current on vbus 0.75 0.80 0.85 v vrd ? srcdef rd detection threshold for source for default current (host_cur1/0 = 01) 1.50 1.60 1.65 v vrd ? src1.5a rd detection threshold for source for 1.5 a current (host_cur1/0 = 10) 1.50 1.60 1.65 v
FUSB301A www. onsemi.com 5 dc and transient characteristics unless otherwise specified: recommended t a and t j temperature ranges. all typical values are at t a = 25 c and v dd = 3.3 v unless otherwise specified. (continued) symbol unit t a = ? 40 to +85 c t j = ? 40 to +125 c parameter symbol unit max. typ. min. parameter vrd ? src3a rd detection threshold for source for 3 a current (host_cur1/0 = 11) 2.45 2.60 2.75 v vra ? snk ra detection threshold for cc pin for sink 0.15 0.20 0.25 v vrd ? def rd default current detection threshold for sink 0.61 0.66 0.70 v vrd ? 1.5a rd 1.5 a current detection threshold for sink 1.16 1.23 1.31 v vrd ? 3.0a rd 3 a current detection threshold for sink 2.04 2.11 2.18 v vvbusthr vbus threshold at which i_vbusok interrupt is triggered 3.7 v current consumption symbol parameter v dd (v) conditions t a = ? 40 to +85 c t j = ? 40 to +125 c unit min. typ. max. unit idisable disabled current 3.0 to 5.5 disabled state 0.35 2.0 a istby unattached sink 3.0 to 5.5 nothing attached 3.5 7.0 a unattached sink + acc, source + acc, or drp nothing attached, internally toggling 5 20 a iattach attach current (less host current) 3.0 to 5.5 attached as a sink 5 15 a attached as a source 10 15 a timing parameters symbol parameter t a = ? 40 to +85 c t j = ? 40 to +125 c unit min. typ. max. unit tccdebounce debounce time for cc (source or accessory) 100 150 200 ms debounce time for cc (sink) 63 75 87 ms tpddebounce debounce time for cc detach detection 10 15 20 ms taccdetect debounce time to detect audioaccessory, or debugaccessory is at- tached 50 100 200 ms terrorrecovery time staying in the errorrecovery state if sent there via the error_rec bit or by a change of modes 25 50 100 ms tvbusondeb debounce time of vbus detection when acting as a sink to signal vbus is present 0.167 0.200 0.375 ms tvbusoffdeb debounce time of vbus detection when acting as a sink to signal vbus has been removed 10 15 20 ms tdrptoggle1 for drp operation, time spent in unat- tached.sink before going to unattached.source state drproggle = 00 35 70 ms drproggle = 01 30 60 drproggle = 10 25 50 drproggle = 11 20 40
FUSB301A www. onsemi.com 6 timing parameters symbol unit t a = ? 40 to +85 c t j = ? 40 to +125 c parameter symbol unit max. typ. min. parameter tdrptoggle2 for drp operation, time spent in unat- tached.source before going to unattached.sink state drproggle = 00 15 30 ms drproggle = 01 20 40 drproggle = 10 25 50 drproggle = 11 30 60 io specifications symbol parameter v dd (v) conditions t a = ? 40 to +85 c t j = ? 40 to +125 c unit min. typ. max. unit host interface pins (id) v olid output low voltage 3.0 to 5.5 i ol = 4 ma 0.4 v host interface pins (i2caddr) v iladdr low ? level input voltage 3.0 to 5.5 0.3v dd v v ihaddr high ? level input voltage 3.0 to 5.5 0.7v dd v host interface pins (int_n) v olintn output low voltage 3.0 to 5.5 i ol = 4 ma 0.4 v i 2 c interface pins ? fast mode sda, scl v ili2c low ? level input voltage 3.0 to 5.5 0.4 v v ihi2c high ? level input voltage 3.0 to 5.5 1.2 v v hys hysteresis of schmitt trigger in- puts 3.0 to 5.5 0.2 v i i2c input current of sda and scl pins 3.0 to 5.5 input voltage 0.26 v to 2 v ? 10 10 a i ccti2c vdd current when sda and scl are high 3.0 to 5.5 input voltage 1.8 v 10 a v olsda low ? level output voltage at 3 ma sink current (open ? drain) 3.0 to 5.5 0 0.3 v c i capacitance for each i/o pin (2) 3.0 to 5.5 10 pf 2. guaranteed by characterization. not production tested. fast mode i 2 c specifications (note 3) (see figure 4) symbol parameter fast mode unit min. max. f scl i2c_scl clock frequency 0 400 khz t hd;sta hold time (repeated) start condition 0.6 s t low low period of i2c_scl clock 1.3 s t high high period of i2c_scl clock 0.6 s t su;sta set ? up time for repeated start condition 0.6 s t hd;dat data hold time 0 0.9 s t su;dat data set ? up time (note 4) 100 ns t r rise time of i2c_sda and i2c_scl signals (note 5) 20*(v dd /5.5v) 250 ns t f fall time of i2c_sda and i2c_scl signals (note 5) 20*(v dd /5.5v) 250 ns
FUSB301A www. onsemi.com 7 fast mode i 2 c specifications (note 3) (see figure 4) (continued) symbol unit fast mode parameter symbol unit max. min. parameter t su;sto set ? up time for stop condition 0.6 s t buf bus ? free time between stop and start conditions 1.3 s t sp pulse width of spikes that must be suppressed by the input filter 0 50 ns 3. guaranteed by characterization. not production tested. 4. a fast ? mode i 2 c bus device can be used in a standard ? mode i 2 c bus system, but the requirement t su;dat 250 ns must be met. this is automatically the case of the device does not stretch the low period of the i2c_scl signal. if such a device does stretch the l ow period i2c_scl signal, it must output the next data bit to the i2c_sda line tr_max + t su;dat = 1000 + 250 = 1250 ns (according to the standard ? mode i 2 c bus specification) before the i2c_scl line is released. 5. cb equals the total capacitance of one bus line in pf. if mixed with high ? speed devices, faster fall times are allowed according to the i 2 c specification. figure 4. definition of timing for full ? speed mode devices on the i 2 c bus i 2 c interface the FUSB301A includes a full i 2 c slave controller. the i 2 c slave fully complies with the i 2 c specification version 6 requirements. this block is designed for fast mode. examples of an i 2 c write and read sequence are shown figure 5 and figure 6 respectively. figure 5. i 2 c write example note: single byte read is initiated by master with p immediately following first data byte. figure 6. i 2 c read example note: if register is not specified master will begin read from current register. in this case only sequence showing in red brack et is needed. register address to read specified single or multi byte read executed from current register location (single byte read is initiated by master with na immediately following first data byte) i 2 c address the i2caddr bit high or low is indicated in bit3 of the slave address shown in table 2.
FUSB301A www. onsemi.com 8 table 2. FUSB301A i 2 c slave address name size (bits) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 slave address 8 0 1 0 0 i2caddr 0 1 r/w register definitions table 3. register map address register name type rst val bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 01 device id ro 12 version id [3:0] revision id [3:0] 0 02 modes r/w 04 drp+acc drp sink+acc sink source+acc source 0 03 control r/w 03 drptoggle host_cur1 host_cur0 int_mask 0 04 manual w/c 00 unatt_snk unatt_src disabled error_rec 0 05 reset w/c 00 sw_res 0 06 ? 0 0f reserved x xx do not use 0 10 mask r/w 00 m_acc_ch m_bc_lvl m_detach m_attach 0 11 status ro 00 orient1 orient0 vbusok bc_lvl1 bc_lvl0 attach 0 12 type ro 00 sink source debugacc audioacc 0 13 interrupt r/c 00 i_acc_ch i_bc_lvl i_detach i_attach 0 14 ? 0 1f reserved x xx do not use 6. do not use registers that are blank. 7. values read from undefined register bits are invalid. do not write to undefined registers. table 4. device id address: 01h reset value: 0 0001_0010 type: read only bit # name size (bits) description 7:4 version id 4 device version id by trim or etc. a_[version id]: 0001 (FUSB301Atmx) 3:0 revision id 4 revision history of each version [revision id]_revc: 0010 table 5. modes address: 02h reset value: 0 0000_0100 type: read/write bit # name size (bits) description 7:6 reserved 2 do not use 5 drp+acc 1 1: configure device as a dual role port (drp) with accessory support 4 drp 1 1: configure device as a dual role port (drp) without accessory support 3 sink+acc 1 1: configure device as a sink with accessory support 2 sink 1 1: configure device as a sink without accessory support 1 source+acc 1 1: configure device as a source with accessory support 0 source 1 1: configure device as a source without accessory support
FUSB301A www. onsemi.com 9 table 6. control address: 03h reset value: 0 xx00_x011 type: read/write bit # name size (bits) description 7:6 reserved 2 do not use 5:4 drptoggle 2 selects different timing for dual role port toggle between unattached. sink state and unattached.source state. 00: 35 ms min. in unattached.sink and 15 ms min. in unattached.- source 01: 30 ms min. in unattached.sink and 20 ms min. in unattached.source 10: 25 ms min. in unattached.sink and 25 ms min. in unattached.source 11: 20 ms min. in unattached.sink and 30 ms min. in unattached.source 3 reserved 1 do not use 2:1 host_cur [1:0] 2 1: controls the pull ? up current when device enabled as a source 00: no current 01: 80 a ? default usb power 10: 180 a ? medium current mode: 1.5 a 11: 330 a ? high current mode: 3 a 0 int_mask 1 1: global interrupt mask to mask all interrupts table 7. manual (note 8) address: 04h reset value: 0 xxxx_0000 type: write/clear bit # name size (bits) description 7:4 reserved 4 do not use 3 unatt_sink (note 9) 1 1: put device in unattached.sink state as defined in the type c spec 2 unatt_source 1 1: put device in unattached.source state as defined in the type c spec 1 disabled (note 10) 1 1: put device in disabled state as defined in the type c spec 0 error_rec 1 1: put device in errorrecovery state as defined in the type c spec 8. if more than one bit is set to ??b1?? simultaneously then an order of priority will be used. 1 st priority is disabled, 2 nd is error_rec, 3 rd is unatt_source, last is unatt_sink. the highest priority bit will take precedence and all other bits will be cleared automatic ally. 9. wait 2 ms between modes = sink and manual = unatt_sink writes. 10. the disabled bit must be manually cleared. table 8. reset address: 05h reset value: 0 xxxx_xxx0 type: write/clear bit # name size (bits) description 7:6 reserved 7 do not use 0 sw_res 1 1: reset the system and i2c register. table 9. mask address: 10h reset value: 0 xxxx_0000 type: read/write bit # name size (bits) description 7:4 reserved 4 do not use 3 m_acc_ch 1 1: mask a change from accessory present to attached accessory
FUSB301A www. onsemi.com 10 table 9. mask (continued) address: 10h reset value: 0 xxxx_0000 type: read/write bit # description size (bits) name 2 m_bc_lvl 1 1: mask a change in i_bc_lvl interrupt bit 1 m_detach 1 1: mask the i_detach interrupt bit 0 m_attach 1 1: mask a change in the i_attach interrupt bit table 10. status address: 11h reset value: 0 xx00_0000 type: read bit # name size (bits) description 7:6 reserved 2 do not use 5:4 orient[1:0] 2 status to indicate which ccx pins has the cc cable connection 11: a fault has occurred during the detection 10: cable cc is connected through the cc2 pin 01: cable cc is connected through the cc1 pin 00: no or unresolved connection detected. 3 vbusok 1 1: status to indicate vbus is in the valid range 2:1 bc_lvl[1:0] 2 thresholds that allow detection of current advertisement on cc line 00: ra or unattached sink 01: rd threshold for sink default current advertisement 10: rd threshold for sink 1.5 a current advertisement 11: rd threshold for sink 3 a current advertisement 0 attach 1 1: attached to a device or accessory of a type shown in the type register table 11. type address: 12h reset value: 0 xxx0_0x00 type: read bit # name size (bits) description 7:5 reserved 3 do not use 4 sink 1 1: indicates a sink has been detected 3 source 1 1: indicates a source has been detected 2 reserved 1 do not use 1 debugacc 1 1: indicates a debug accessory has been detected 0 audioacc 1 1: indicates a audio accessory has been detected table 12. interrupt0 address: 13h reset value: 0 xxxx_x000 type: write/clear bit # name size (bits) description 7:4 reserved 4 do not use 3 i_acc_ch 1 1: interrupt flagged when a change from accessory present to audio ac- cessory or debug accessory occurs. 2 i_bc_lvl 1 1: interrupt flagged when a change in bc_lvl advertised current level has occurred
FUSB301A www. onsemi.com 11 table 12. interrupt0 (continued) address: 13h reset value: 0 xxxx_x000 type: write/clear bit # description size (bits) name 1 i_detach 1 1: interrupt flagged when a device or accessory has been detached 0 i_attach 1 1: interrupt flagged when a device or accessory of type indicated in the type register has been attached on semiconductor is licensed by the philips corporation to carry the i 2 c bus protocol.
x2qfn12 1.6x1.6, 0.4p case 722ad issue o date 31 oct 201 6 mechanical case outline package dimensions http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: new standard: description: 98aon13693g on semiconductor standard x2qfn12 1.6x1.6, 0.4p electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon13693g page 2 of 2 issue revision date o released for production from fairchild tmlp12a to on semicon- ductor. req. by c. tan. 31 oct 2016 ? semiconductor components industries, llc, 2016 october, 2016 ? rev. o case outline number : 722ad on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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